Thema:	 [MESSDEV] Extremely subtle bug in cpu/m6809/6809ops.c
Datum:	15.06.00 14:29:23 (MEZ) - Mitteleurop. Sommerzeit
From:	nathan@summsoft.com
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Datei:  patch.zip (7523 Bytes)
DL-Zeit (32000 Bit/s): < 1 Minute


I found an extremely subtle bug in the CPU core.

Essentially, the CLR instruction also performs a read on the target
address (in non register mode).  Similarly, TST performs a write.
This caused a bug in a CoCo 3 program because CLR was being used on
memory mapped IO where reading performed an operation.  To quote John
Kowalski, (a CoCo hardware guru):

---
A number of 6809 opcodes don't *strictly* do what they imply that they
do.
One of them is the CLR opcode.  Internally, CLR is lumped together
with
other 'read, modify, write' opcodes like
NEG,COM,LSR,ROR,ASR,ASL,ROL,DEC and
INC.   So, instead of just writing a $00 like the name implies, CLR
*actually* reads the memory location, THEN writes a zero to it.
So, in this case, since CLR actually reads the register first, it
resets the
interrupt.

Another 6809 opcode that works like a 'read, modify, write' is TST.
Instead
of just reading a memory location and testing the value, it also
writes it
*back* to memory.  That's why CLR and TST have higher cycle counts
than
you'd expect.  They perform unncessary operations.  There are some
other
opcodes that do things like that, but mostly they're unnessary reads
so they
probably aren't an issue.

To fix that....well, you'd have to change the 6809 emulator itself to
emulate the extra operations.  Until then, I think your solution is
good.
It probably won't break any programs.
---

I've taken the liberty of modifying cpu/m6809/6809ops.c.  Any chance
that this file could be submitted to MAMEdev?
(See attached file: patch.zip)

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From: nathan@summsoft.com
Subject: [MESSDEV] Extremely subtle bug in cpu/m6809/6809ops.c
To: messdev@synthcom.com
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