8 32-bit Data registers DO-D7
7 32-bit Address registers AO-A7
2 32-bit stack pointers
24-bit Program counter
16-bit Status register
We immediately see that the internal architecture of the
processor is 32-bit. This means whenever an internal arithmetic
operation is carried out then 32 bits are added, subtracted,
anded, shifted or whatever. Thus the limitations of 8-bit
arithmetic are overcome.
There are now 8 general purpose data registers so that many more values can be kept in the processor registers reducing the frequency of memory accesses. All these data registers are equivalent to the accumulators in the 6809 and can be used for all arithmetic and logical instructions. In addition data values can be specified to be short (8-bit) normal (16-bit) or long (32- bit) in order to optimise the processing speed when the full 32-bit length is not required.
All registers handling addresses are incresed in length to at least 24-bits thus allowing 16MBytes of memory to be addressed. Since arithmetic operations can be carried out on the general address registers they are made 32-bit for compatibility with the data registers. The stack pointer is effectively the eighth address register (and is addressed as such) but it can be switched from system to user and has the special functions associated with a stack pointer.
The number of address registers, which can be used as base registers, index registers etc means that a number of pointers to tables can be kept in the processor at a time.
The 6809 has a synchronous bus transfer mechanism which leads to simple system design but means that the whole system runs at the rate of the slowest devices. Synchronous means that transfers are controlled by a clock and that devices must be able to generate or receive data within a clock period. If a device takes longer than a clock period to respond then the system will not work. All devices in the system are therefore chosen to have similar access times. In a 68000 system access times can vary thus allowing greater flexibility in system design. for example very fast, high-cost memory can be used where access is frequent while cheaper slower memory can be used for infrequently accessed areas. To enable this to work the 68000 has an asynchronous bus.
The asynchronous bus works using two control signals in the same sort of handshaking arrangement that we saw using the VIA. If we take a memory write cycle as an example; the-processor sets R/W low to indicate a write cycle, sets the address on the address bus and the data on the data bus. The AS (address strobe), UDS (upper data strobe) and LDS (lower data strobe) all go low to indicate valid data on the address bus, and on both halves of the data bus. The processor then waits for a low signal on DTACK (data transfer acknowledge) which is generated at by the memory device when it has received and latched the data. The processor proceeds on the following clock pulse. A transfer like this can take anything from 4 clock cycles upwards depending on the speed of the memory. The clock rate depends on the version of the processor 4,6,8,10,12.5 and 16 MHz versions have been made. The 'standard' at present is 10MHz so each clock period is 100ns.
This type of bus arrangement has many advantages in terms of speed but it increases the complexity of the system because there are more control signals and memory has to generate the acknowledge signal. There is also a problem which arises when an invalid address is output i.e. one where no memory is present. In a 6809 system the data lines float high and the value $FF is read. In 68000 system no DTACK will be generated and so the processor will wait indefinitely. Clearly this cannot be allowed to happen and so a 'watchdog' timer must be included which monitors the length of time that elapses before DTACK is generated. If no DTACK appears for, say, 10 ms then a BERR (bus error) signal is sent to the processor. This is effectively an interrupt which has its own restart address and allows the monitor program or operating system to take appropriate action such as generating an error message. Again this makes the system more complex but has the added advantage that this situation is detected where in a 6809 system it would not be.
In order to allow standard interface chips, such as VIA or PIA to be used a synchronous bus control is also permitted where the processor generates an E signal. When such a device is addressed it tells the processor it is such a device by taking VPA (valid peripheral address) low. The transfer is then synchronised to the E clock.
Similarly ADD can be used with data or address registers and with small numbers coded in the instruction. It thus replaces all increment instructions as well as ADD instructions in the 6809. The same applies to subtract instructions which replace decrement.
In addition to the unsigned multiply instruction available in the 6809 there is signed multiplication of up to 32-bitdata as well as both signed and unsigned division. Clearly multiplication of 32-bit numbers can generate a 64-bit result which has to be stored in two data registers and would require 4 16-bit memory locations.
Most of these instructions can be used with byte, word, or long word data formats and in some cases bits as well. In addition there are 14 addressing modes which can be used with most instructions that reference memory.
Immediate - as in M6809
Address register indirect - the address is contained in an address register - equivalent to indexed. Is provided with postincrement and predecrement as in 6809
Address register indirect with displacement - The address is computed from the contents of an address register with a fixed displacement added. This is base register addressing which has some similarities with the indexed addressing in 6809.
Address register indirect with index - This allows base register addressing to be used in conjunction with indexed addressing. This is essential if real base register addressing is to be implemented.
Program counter with displacement - This is equivalent to relative addressing and provides an alternative to base register.
Program counter with index - Relative addressing with indexed - again essential for truly relocatable programs.