Programmable Sound Generator (AY-3-8912)

Features
* Full Software Control of Sound Generation
* Interface to Most 8-Bit and 16-Bit Microprocessors
* Three Independently Programmed Analog Outputs
* One 8-Bit General Purpose I/O Port

Description
The AY-3-8912 Programmable Sound Generator (PSG) is
a LSI Circuit which can produce a wide variety of complex sounds
under software control. The AY-3-8912 is manufactured in
the General Instrument N-Channel Ion Implant Process. Operation
requires a single +5V power supply a TTL compatible clock, and a
microprocessor controller such as the General Instrument 16-bit
CP1610 or one of the PIC1650 series of 8-bit microcomputers.

The PSG is easily interfaced to any bus oriented system. Its flexibility
makes it useful in applications such as music systems, sound
effects generation, audible alarms, tone signalling and FSK modems.
The analog sound outputs can provide 4 bits of logarithmic
digital to analog conversion, greatly enhancing the dynamic range of
the sounds produced.

In order to perform sound effects while allowing the processor to
continue its other tasks, the PSG can continue to produce sound
after the initial commads have been given by the control processor.
The fact that realistic sound production often involves more than one
effect is satisfied by the three independently controllable channels
available in the PSG.

All of the circuit control signals are digital in nature and intended to
be provided directly by a microprocessor/microcomputer. This
means that one PSG can produce the full range of required sounds
with no change in external circuitry. Since the frequency response of
the PSG ranges from sub-audible at its lowest frequency to post-
audible at its highest frequency, there are a few sounds which are
beyond reproduction with only the simplest electrical connections.

Since most applications of a microprecessor/PSG system would also
require interfacing between outside world and the microprocessor
this facility has been designed into the PSG. The AY-3-8912 has
one port and 28 leads.

PIN CONFIGURATION
28 LEAD DUAL IN LINE
AY-3-8912
                            Top View
                       ___________________
                      |       \___/       |
    ANALOG CHANNEL C -|1                28|- DA0
                      |                   |
              TEST 1 -|2                27|- DA1
                      |                   |
           Vcc (+5V) -|3                26|- DA2
                      |                   |
    ANALOG CHANNEL B -|4                25|- DA3
                      |                   |
    ANALOG CHANNEL A -|5                24|- DA4
                      |                   |
            Vss(GND) -|6                23|- DA5
                      |                   |
                IOA7 -|7                22|- DA6
                      |                   |
                IOA6 -|8                21|- DA7
                      |                   |
                IOA5 -|9                20|- BC1
                      |                   |
                IOA4 -|10               19|- BC2
                      |                   |
                IOA3 -|11               18|- BDIR
                      |                   |
                IOA2 -|12               17|- A8
                      |                   |  _____
                IOA1 -|13               16|- RESET
                      |                   |
                IOA0 -|14               15|- CLOCK
                      |___________________|

PIN FUNCTIONS

DA7-DA0 (input/output/high impedance)
Data/Address 7--0:  pins 21--28
These 8 lines comprise the 8-bit bidirectional bus used by the
microprocessor to send both data and addresses to the PSG and to
recieve data from the PSG. In the data mode, DA7--DA0 correspond
to Register Array bits B7-B0. In the address mode, Da3--Da0 select
the register number (0--17) and a DA7--DA4 in conjunction with
address inputs A8 for high order address (chip select).

A8 (input): pin 17
Address 8
These "extra" address bit is made available to enable the positioning
of the PSG (assigning a 16 word memory space) in a total 512
word memory area rather than a 256 word memory area as defined
by address bits DA7--DA0 alone. If the memory size does not require
the use of this extra address line it may be left unconnected as
it is provided with an on-chip pull-up resistor. In "noisy" environments,
however, it is recommended that A8 is tied to +5V, if it is not to be
used.
_____
RESET (input): pin 16
For initialization/power-on purposes, applying a logic "0" (ground)
to the reset pin will reset all registers to "0". The reset pin is provided
with an on-chip pull-up resistor.

CLOCK (input): pin 15
This TTL-compatible input sipplies the timing reference for the
Tone, Noise and Envelope Generators.

BDIR, BC2, BC1 (inputs: pins 18, 19, 20
Bus DIRection, Bus Control 2, 1
These bus control signals are generated directly by the CP1610
series of microprocessors to control all external and internal bus
operations in the PSG. When using a processor other than the
CP1610, these signals can be provided either by comparable bus
signals or by simulating the signals on I/O lines or the processor. The
PSG decodes these signals as illustrated in the follwing:

BDIR BC2 BC1   CP1610         PSG
              FUNCTION      FUNCTION
  0   0   0     NACT        INACTIVE. See 010 (IAB).
  0   0   1     ADAR        LATCH ADDRESS, See 111 (INTAK).
  0   1   0     IAB         INACTIVE. The PSG/CPU bus is inactive DA7--DA0
                            are in high impedance state.
  0   1   1     DTS         READ FROM PSG. This signal causes the contents
                            of the register which is currently addressed to
                            appear on the PSG/CPU bus. DA7--DA0 are in the
                            output mode.
  1   0   0     BAR         LATCH ADDRESS. See 111 (INTAK).
  1   0   1     DW          INACTIVE. See 010 (IAB).
  1   1   0     DWS         WRITE TO PSG. This signal indicates that the bus
                            contains register data which should be latched into
                            the currently addressed register. DA7--DA0 are in
                            the input mode.
  1   1   1     INTAK       LATCH ADDRESS. This signal indicates that the bus
                            contains a register address which should be latched
                            in the PSG. DA7--DA0 are in input mode.

While interfacing to a processor other than the CP1610 would simply
require simulating the above decoding, the redundancies in the PSG
functions vs bus control signals can be used to advantage in that
only four of the eight possible decoded bus functions are required by
the PSG. This could simplify the programming of the bus control
signals to the following, which would only require that the processor
generate two bus control signals (BDIR and BC1, with BC2 tied to
+5V).

BDIR BC2 BC1      PSG
                FUNCTION
  0   1   0     INACTIVE.
  0   1   1     READ FROM PSG.
  1   1   0     WRITE TO PSG.
  1   1   1     LATCH ADDRESS.

ANALOG CHANNEL A, B, C (outputs): pins 5, 4, 1
Each of these signals is the output of its corresponding D/A
Converter, and provides an up to 1V peak-peak signal representing
the complex sound waveshape generated by the PSG.

IOA7--IOA0 (input/output): pins 7--14
Input/Output A7--A0
This parallel input/output port provides 8 bits of
prarllel data to/from the PSG/CPU bus from/to any external devices
connected to the IOA pins. Each pin is provided with an on-chip
pull-up resistor, so that when in the "input" mode, all pins will
read normally high. Therefore, the recommended method for scanning
external switches would be to ground the input bit.

TEST 1: pin 2
This pin is for General Instrument test purposes only and should
be left open - do not use as tie-point.

Vcc: pin 3
Nominal +5Volt power supply to the PSG.

Vss: pin 6
Ground reference for the PSG.


ARCHITECTURE

The AY-3-8912 is a register oriented Programmable Sound
Generator (PSG). Communication between the processor and the
PSG is based on the concept of memory-mapped I/O. Control
commands are issued to the PSG by writing to 16 memory-mapped
rigisters. Each of the 16 registers within the PSG is also readable
so that the mircroprocessor can determine, as necessary, present
states or stored data values.

All functions of the PSG are controlled through the 16 registers which
once programmed, generate and sustain the sounds, thus freeing the
system processor for other tasks.

REGISTER ARRAY
The principle element of the PSG is the array of 16 read/write control
registers. These 16 registers lock to the CPU as a block of memory
and as such occupy a 16 word block out of 512 possible addresses.
The 9 address bits (8 bits on the common data/address bus, and 1
separate address bit A8) are decoded as follows:

   ___ ___ ___ ___ ___ ___ ___ ___ ___
  |   |   |   |   |   |   |   |   |   |
  | A8|DA7|DA6|DA5|DA4|DA3|DA2|DA1|DA0|
  |___|___|___|___|___|___|___|___|___|
  |   |   |   |   |   |   |   |   |   |
  | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
  |___|___|___|___|___|___|___|___|___|
                THRU
   ___ ___ ___ ___ ___ ___ ___ ___ ___
  |   |   |   |   |   |   |   |   |   |
  | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
  |___|___|___|___|___|___|___|___|___|
   \_________________/ \_____________/
          \/                 \/
        HIGH ORDER        LOW ORDER
      (Chip Select)     (Register No.)

The four low order address bits select one of the 16 registers
(R0--R17). The 5 high order address bits function as "chip selects"
to control the tri state bidirectional buffers (when the high order
address bits are "incorrect", the bidirectional buffers are forced to a
high impedance state). High order address bit A8 is fixed in the
PSG design to recognize a 1 code; high order address bits DA7--DA4
may be maskk-programmed to any 4-bit code by a special order
factory mask modification. Unless otherwise specified, address bits
DA7--DA4 are programmed to recognize only a 0000 code. A valid
high order address latches the register address (the low order 4 bits)
in the Register Address Latch/Decode block. A latched address will
remain valid until the receipt of a new address, enabling multiple
reads and writes of the same register contents without the need for
redundant re-addressing.

Conditioning of the Register Address Latch/Decode and Bidirectional
Buffers to recognize the bus function required (anactive,
latch address, write data, or read) is accomplished by the Bus Control
Decode block.

SOUND GENERATING BLOCKS
The basic blocks in the PSG which produce the programmed sounds
include:
Tone Generator          produce the basic square tone frequencies
                        for each channel (A, B, C)

Noise Generator         produces a frequency modulated pseudo
                        random pulse width square wave output.

Mixers                  combine the outputs of the Tone Generators
                        and the Noise Generator. One for each channel
                        (A, B, C)

Amplitude Control       provides the D/A Converters with either a
                        fixed or variable amplitude pattern. The fixed
                        amplitude is under direct CPU control; the
                        variable amplitude is accomplished by using
                        the output of the Envelope Generator.

Envelope Generator      Produces an envelope pattern which can be
                        used to amplitude modulate the output of
                        each Mixer

D/A Converters          the three D/A Converters each produce up to
                        a 16 level output signal as determined by the
                        Amplitude Control

I/O PORT
One additional block is shown in the PSG Block Diagramm which
has nothing directly to do with the production of sound - this is
an I/O Port (A). Since virtually all uses or microprocessor-based
sound would require interfacing between the outside world and the
processor, this facility has been included in the PSG.
Data to/from the CPU bus may be read/written to the 8-bit I/O Port
without affecting any other function of the PSG. The I/O
Port is TTL-compatible and is provided with internal pull-ups on
each pin.

OPERATION

Since all functions of the PSG are controlled by the processor
via a series of regiser loads, a detailed description of the PSG
operation can best be accomplished by relating each PSG function to
the control of its corresponding register. The function of creating or
programming a specific sound or sound effect logically follows the
control sequence listed:

        Operation               Registers     Function
Tone Generator Control           R0--R5       Program tone peroids.

Noise Generator Control            R6         Program noise peroid.

Mixer Control                      R7         Enable tone and/or noise
                                              on selected channels.

Amplitude Control               R10--R12      Select "fixed" or "envelope-
                                              variable" amplitudes.

Envelope Generator Control      R13--R15      Program envelope period
                                              and select envelope pattern.

Tone Generator Control
(Registers R0, R1, R2, R3, R4, R5)
The frequency of each square wave generated by the three Tone
Generators (one each for Channels A, B, and C) is obtained in the
PSG by first counting down the input clock by 16, the by further
counting down the result by the programmed 12-bit Tone Period
value. Each 12-bit value is obtained in the PSG by combining the
contents of the relative Coarse and Fine Tune registers, as illustrated
in the following:

   Coarse Tune Registers     Channel            Fine Tune Register
          R1                    A                      R0
          R3                    B                      R2
          R5                    C                      R4

   B7 B6 B5 B4 B3 B2 B1 B0                      B7 B6 B5 B4 B3 B2 B1 B0
   \_________/ I          \                    /                      /
       \/      I            \                /                      /
    NOT USED   I             I ____________/                      /
             /               I/                              ___/
            TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
                12-bit Tone Period (TP) to Tone Generator

Noise Generator Control
(Register R6)
The frequency of the noise source is obtained in the PSG by first
counting down the input clock by 16, then by further counting down
the result by the programmed 5-bit Noise Period value. This 5-bit
value consists of the lower 5-bits (B4-B0) of register R6, as
illustrated in the following:

               Noise Period Register R6

               B7 B6 B5 B4 B3 B2 B1 B0
               \______/ \___________/
                  \/         \/
               NOT USED   5-bit Noise Period (NP)
                          to Noise Generator

Mixer Control-I/O Enable
(Register R7)                     ______
Register R7 is a multi functional Enable register which controls the
three Noise/Tone Mixers and the general purpose I/O Port.

The Mixers, as previously described, combine the noise and tone
frequencies for each of the three channels. The determination of
combining neither/either/both noise and tone frequencies on each
channel is made by the stae of bits B5-B0 or R7.

The direction (input or output) of the general purpose I/O Port
(IOA) is determined by the state of bit B6 or R7.

These functions are illustrated in the following:

               Mixer Control-U/O Enable Register R7

               B7 B6 B5 B4 B3 B2 B1 B0
   NOT USED____/  I  \______/ \______/
                  I   __\/       \/_______
    ____________ /   I___________        I__________
    Input Enable     Noise Enable        Tone Enable  <-- Function
    I/O Port A        C   B   A           C   B   A   <-- Channel

Amplitude Control
(Registers R10, R11, R12)
The amplitudes of the signals generated by each of the three D/A
Converters (one each for Channels A, B, and C) is determined by the
contents of the lower 5 bits (B4--B0) of registers R10, R11, and R12 as
illustrated in the follwing:

       Amplitude Control Register    Channel
                 R10                   A
                 R11                   B
                 R12                   C

               B7 B6 B5 B4 B3 B2 B1 B0
               \______/  I \________/
                  \/     I     \/
               NOT USED  I     L3 L2 L1 L0
                         I     4-bit "fixed" amplitude Level.
                         I
                         M
                   amplitude "Mode"

Envelope Generator Control
(Registers R13, R14, R15)
To accomplish the generation of fairly complex envelope patterns,
two independent methods of control are provided in the PSG: first, it
is possible to vary the frequency of the envelope using registers R13
and R14; and second, the relative shape and cycle pattern of the
envelope can be varied using register R15. The following paragraphs
explain the details of the envelope control functions, describing
first the envelope period control and then the envelope shape/cycle
control.

ENVELOPE PERIOD CONTROL (Registers R13, R14)
The frequency of the envelope is obtained in the PSG by first
counting down the input clock by 256, then by further counting down
the result by the programmed 16-bit Envelope Peroid value. This
16-bit value is obtained in the PSG by combining the contents of the
Envelope Coarse and Fine Tune registers, as illustrated in the
following:

       Envelope                                     Envelope
   Coarse Tune Registers                        Fine Tune Register
          R14                                          R13

   B7 B6 B5 B4 B3 B2 B1 B0 ____                B7 B6 B5 B4 B3 B2 B1 B0
  /                            \              /                      I
 I                               \          /                        I
 I                                 \      /                          I
 I                                   \  /                            I
 TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
            16-bit Envelope Period (EP) to Envelope Generator

ENVELOPE SHAPE/CYCLE CONTROL (Register R15)
The Envelope Generator further counts down the envelope frequency
by 16, producing a 16-state per cycle envelope pattern as
defined by its 4-bit counter output, E3, E2, E1, E0. The particular shape
and cycle pattern of any desired envelope is accomplished by
controlling the count pattern (count up/count down) of the 4-bit
counter and by defining a single-cycle or repeat-cycle pattern.

This envelope shape/cycle control is contained in the lower 4 bits
(B3--B0) of register R15. Each of these 4 bits controls a function in
the envelope generator, as illustrated in the following:

        Envelope Shape/Cycle Control Register (R15)

               B7 B6 B5 B4 B3 B2 B1 B0     Function
               \_________/ I  I  I  I_____ Hold      \
                  \/       I  I  I________ Alternate I To Envelope
               NOT USED    I  I___________ Attack    I Generator
                           I______________ Continue  /

I/O Port Data Store
(Register R16)
Register R16 functions as intermediate data storage register
between PSG/CPU data bus (DA0--DA7) and the I/O port (IOA7--IOA0).
Using register 16 for the transfer of I/O data has no effect on
sound generation.

D/A Converter Operation
Since the primary use of the PSG is to produce sound for the highly
imperfect amplitude detection mechanism of the human ear, the D/A
conversion is performed in logarithmic steps with a normalized
voltage range of from 0 to 1 Volt. The specific amplitude control of
each of the three D/A Converters is accomplished by the three sets of
4-bit outputs of the Amplitude Control block, while the Mixer outputs
provide the base signal frequency (Noise and/or Tone).
